DPSA: A Framework for Dataflow Aware Precision Scalable DNN Accelerator Design

Many hardware architectures have been proposed to support such computation that bit width or precision is low and scalable, especially quantized deep neural networks (DNN). However, these works lack the consideration of dataflow, which means how the batches of data of deep neural network transfer and compute on the hardware efficiently. Besides, research focusing on dataflow lacks the consideration of the precision scalable situation. Meanwhile, these architectures and their dataflow are designed manually and will take much effort to update given that the DNNs evolve rapidly. To solve these shortcomings, we propose a framework to provide efficient precision-scalable DNN accelerators design parameters and dataflows on them automatically. We model the hardware structures and dataflows by intermediate representations. Then, we perform a design space exploration with the modeling and search for optimum hardware and dataflow design. Experimental results show that our designs are competitive to manually designed structures and hand-optimized programs. In some cases, our results exceed a state-of-the-art hardware accelerator in performance by an average of 1.19x.