Research on the thermal properties and interface resistance of multilayer multiscale semiconductor structures

The investigation of the thermal characteristics of high-power chips is mainly based on Fourier's law, and it does not adequately explore the microscale effects of the heat transfer process. In pursuit of a more profound comprehension of the size-dependent traits manifesting in the thermal conduction across multilayer, multiscale materials, this manuscript incorporates the phonon transport's scattering mismatch attributes, introducing a MBDE methodology aimed at delineating the thermal characteristics inherent to multilayer, multiscale structures. This approach was applied to elucidate the energy transfer dynamics among bi-layer (Si/Si, Diamond/Si, and Cu/Si) configurations of differing scales. To enhance thermal transfer efficiency, this work prioritizes the minimization of interface thermal resistance and system temperature gradients as optimization objectives, employing a genetic algorithm to identify scales favorable for energy transfer. The results indicate: 1) An increase in the Knudsen number (Kn) correlates with a more pronounced energy discontinuity at the interface, thereby elevating the interface thermal resistance; 2) The disparate material combinations exhibit varied energy transfer efficiencies, where the phononic compatibility between Cu/Si is inferior to that of Diamond/Si, culminating in a notably larger energy discontinuity and, consequently, augmented energy transfer losses for Cu/Si interfaces; 3) Through the application of a genetic algorithm, it was determined that transitioning from Kn1 to Kn2 yields an optimal thermal conduction scenario, characterized by an interface thermal resistance of 1.83 and a comprehensive temperature gradient of 6.69. This work holds significant implications for guiding the thermal design of high-power integrated chips.