A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V _FC _res figure of merit

A silicon carbide p-channel insulated gate bipolar transistor (IGBT) with higher breakdown voltage (BV) and low V-F center dot C- res figure of merit (FOM) has been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction FET (JFET) area and increases the gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (C-res) and gate oxide electric field (E ox). The proposed structure notably lowers E ox below 3 MV cm(-1) while elevating the BV to 16.6 kV. A new FOM of V-F center dot C- res res is defined to evaluate the trade-off between the on-state and the C res characteristics. The experimental results demonstrate that a lower V-F center dot C- res res FOM of 0.369 V center dot pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional current spreading layer IGBT. Meanwhile, the simulated turn-on and turn-off times of the proposed IGBT are reduced by 29.4% and 20%, respectively.