SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS)(2024)
Abstract
Systolic array has emerged as a prominent architecture for Deep Neural
Network (DNN) hardware accelerators, providing high-throughput and low-latency
performance essential for deploying DNNs across diverse applications. However,
when used in safety-critical applications, reliability assessment is mandatory
to guarantee the correct behavior of DNN accelerators. While fault injection
stands out as a well-established practical and robust method for reliability
assessment, it is still a very time-consuming process. This paper addresses the
time efficiency issue by introducing a novel hierarchical software-based
hardware-aware fault injection strategy tailored for systolic array-based DNN
accelerators.
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Key words
hardware accelerator,systolic array,deep neural networks,fault simulation,reliability,resilience assessment
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