A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration

This work presents an agilely designed high-speed energy-efficient Die-to-Die interconnect PHY for silicon interposer based 2.5D integration. Due to the S-parameter of an interconnect is too complex for digital level analysis, a compact RC equivalent circuit model is discussed in this work. The model method works up-to 4 GHz, by comparing with the S-parameter results extracted by commercial 3D electromagnetic field solver. A termination-free die-to-die interconnect transceiver is proposed, where transmitters, receivers and clock modules are all implemented by standard cells, whose layout is generated by commercial digital physical EDA tools. A 28 nm prototype is developed and simulated. It maximally consumes 13.03 mW under 6.4-Gbps data, separately supplied by 0.8 V for logic and 0.5 V for TX drivers and RX front-ends. It achieves an power efficiency of 0.41 pJ/bit with 0.55-UI eye-diagram opening for 2.35 mm die-to-die distance, and the area of the layout in this work is only 686 μm2.