Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies

Design Technology Co-optimization (DTCO) and System Technology Co-optimization (STCO) have become essential techniques to sustain Moore's law, while the geometric scaling has slowed down in the last decade. With newtechnology nodes are on the horizon, the anticipated scaling boost faces a potential hindrance known as the "pin density wall". This challenge arises from the shrinking cell area and the intricate 3D structure of advanced technology nodes, which limits the options for pin accessibility. Consequently, the advantages of cell area shrinkage in given existing advanced architectures may not translate well to block-level design. To address this issue, additional design methodologies regarding routability need to be explored. In this work, we will describe the scope and potential benefits of different design knobs for standard cell design, device architectures, and block-level placement and route. In addition, we will cover the challenges and future research directions by investigating physical space constraints, cell design automation flow, and existing design tool limitations.