CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost
2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)(2024)
摘要
We propose a new RowHammer mitigation mechanism, CoMeT, that prevents
RowHammer bitflips with low area, performance, and energy costs in DRAM-based
systems at very low RowHammer thresholds. The key idea of CoMeT is to use
low-cost and scalable hash-based counters to track DRAM row activations. CoMeT
uses the Count-Min Sketch technique that maps each DRAM row to a group of
counters, as uniquely as possible, using multiple hash functions. When a DRAM
row is activated, CoMeT increments the counters mapped to that DRAM row.
Because the mapping from DRAM rows to counters is not completely unique,
activating one row can increment one or more counters mapped to another row.
Thus, CoMeT may overestimate, but never underestimates, a DRAM row's activation
count. This property of CoMeT allows it to securely prevent RowHammer bitflips
while properly configuring its hash functions reduces overestimations. As a
result, CoMeT 1) implements substantially fewer counters than the number of
DRAM rows in a DRAM bank and 2) does not significantly overestimate a DRAM
row's activation count.
Our comprehensive evaluations show that CoMeT prevents RowHammer bitflips
with an average performance overhead of only 4.01
workloads for a very low RowHammer threshold of 125, normalized to a system
with no RowHammer mitigation. CoMeT achieves a good trade-off between
performance, energy, and area overheads. Compared to the best-performing
state-of-the-art mitigation, CoMeT requires 74.2x less area overhead at the
RowHammer threshold 125 and incurs a small performance overhead on average for
all RowHammer thresholds. Compared to the best-performing low-area-cost
mechanism, at a very low RowHammer threshold of 125, CoMeT improves performance
by up to 39.1
freely available at https://github.com/CMU-SAFARI/CoMeT.
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关键词
Low Cost,Lower Performance,Energy Cost,Average Performance,Hash Function,High Overhead,Low Energy Cost,Area Overhead,Performance Overhead,Low Values,Graphene,False Positive Rate,Average Energy,Data Streams,Key Observation,Activity Counts,Memory Control,Storage Cost,Hardware Implementation,Frequent Items,Processor Chip,Mitigation Techniques,Low Overhead,Design Space Exploration,Two-dimensional Array,Counter Value,Extended Version,Fewer Activities,System Performance Degradation,Greater Than Or Equal
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