A Method to Reduce PDN Impedance Based on Multi-capacitor Loop Coupling

As the target impedance of the power delivery network decreases, the demand for output decoupling capacitors proportionally increases. Parasitic inductance of the vias connecting the output capacitors to the motherboard has a more serious impact on the impedance design of power deliver network. To solve this problem, this letter proposes a novel layout method to reduce the value of parasitic inductance associated with the vias. The proposed method utilizes the coupling effect between the vias to reduce the equivalent inductance. Therefore, the proposed method is not only simple and easy to implement, but also saves space and cost by reducing the number of decoupling capacitors. Two 200-W experimental prototypes were fabricated to compare the conventional solution with the proposed reverse coupling method. The decoupling capacitance of the prototype using the reverse-coupled structure is 25.6% lower than the prototype using conventional forward-coupled method.