A 21.8-41.6-GHz Low Jitter and High FoM_j Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

In this article, a wideband millimeter-wave (mm-wave) fast-locking subsampling phase-locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM $_{\bm{j}}$ ) is proposed. A quadrature subsampling phase detector (QSSPD)-based dead zone automatic controller (DZAC) is introduced for fast locking. Such DZAC eliminates the long locking time caused by the dead zone of frequency-locked loop (FLL) while maintaining low in-band phase noise of subsampling loop (SSL). The mm-wave quad-mode oscillator is integrated in the FL-SSPLL to achieve a wide frequency range. The proposed FL-SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.18 mm $<^>2$ . Measurements exhibit a wide output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The FL-SSPLL achieves a 62.7-79.1-fs root-mean-square (rms) jitter across the whole frequency range. The total power consumption is 18.3-23.6 mW, leading to FoM(j) from -248.3 to -251.4 dB. Meanwhile, the FL-SSPLL features a robust lock acquisition and achieves less than 1.5-mu s locking time.