Inflection Points in GAA NS-FET to C-FET Scaling Considering Impact of DTCO Boosters

Complimentary FETs (C-FETs) enable aggressive standard cell height reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP). We extensively benchmark nanosheet (NS)-based C-FETs against gate-all-around (GAA) NS FETs across range of metal pitches (MPs) tracking their power, performance, and area (PPA). The impact of back-end of line (BEoL) RC, new materials, and various device boosters is further explored. Four-track C-FET designed with 20-nm MP offers 62% smaller area and provides 28% extra speed at isopower (S@P) over reference NS-FET device.