Test Cost Reduction for VLSI Adaptive Test With K-Nearest Neighbor Classification Algorithm

Ensuring the impeccable quality of integrated circuits (ICs) is of utmost importance to the customers. However, the increasing scaling of advanced nanoscale circuits has resulted in also increased cost of tests. In order to optimize test cost without compromising IC quality, it is imperative to reduce test time. Addressing the issue of prolonged test duration, associated with conventional full-pattern tests approaches, this paper introduces a novel and efficient pattern selection method known as stepwise k-nearest neighbors (KNN). By harnessing the power of a classification model, this method selectively identifies and applies only the most potent patterns, that are likely to lead to test failures. This approach dramatically expedites the testing process, resulting in substantial time savings. Experimental results showcase an impressive 27% enhancement in the accuracy of the proposed approach compared to Support Vector Machine (SVM) techniques. This signifies the effectiveness and superiority of the presented method in enhancing both the efficiency and reliability of IC testing.