Efficient Fault Detection Architectures for Modular Exponentiation Targeting Cryptographic Applications Benchmarked on FPGAs
CoRR(2024)
摘要
Whether stemming from malicious intent or natural occurrences, faults and
errors can significantly undermine the reliability of any architecture. In
response to this challenge, fault detection assumes a pivotal role in ensuring
the secure deployment of cryptosystems. Even when a cryptosystem boasts
mathematical security, its practical implementation may remain susceptible to
exploitation through side-channel attacks. In this paper, we propose a
lightweight fault detection architecture tailored for modular exponentiation, a
building block of numerous cryptographic applications spanning from classical
cryptography to post quantum cryptography. Based on our simulation and
implementation results on ARM Cortex-A72 processor, and AMD/Xilinx Zynq
Ultrascale+, and Artix-7 FPGAs, our approach achieves an error detection rate
close to 100
approximately 7
architecture. To the best of our knowledge, such an approach benchmarked on ARM
processor and FPGA has not been proposed and assessed to date.
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