Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips
CoRR(2024)
摘要
RISC-V open-source systems are emerging in deployment scenarios where safety
and security are critical. OpenTitan is an open-source silicon root-of-trust
designed to be deployed in a wide range of systems, from high-end to deeply
embedded secure environments. Despite the availability of various cryptographic
hardware accelerators that make OpenTitan suitable for offloading cryptographic
workloads from the main processor, there has been no accurate and quantitative
establishment of the benefits derived from using OpenTitan as a secure
accelerator. This paper addresses this gap by thoroughly analysing strengths
and inefficiencies when offloading cryptographic workloads to OpenTitan. The
focus is on three key IPs - HMAC, AES, and OpenTitan Big Number accelerator
(OTBN) - which can accelerate four security workloads: Secure Hash Functions,
Message Authentication Codes, Symmetric cryptography, and Asymmetric
cryptography. For every workload, we develop a bare-metal driver for the
OpenTitan accelerator and analyze its efficiency when computation is offloaded
from a RISC-V application core within a System-on-Chip designed for secure
Cyber-Physical Systems applications. Finally, we assess it against a software
implementation on the application core. The characterization was conducted on a
cycle-accurate RTL simulator of the System-on-Chip (SoC). Our study
demonstrates that OpenTitan significantly outperforms software implementations,
with speedups ranging from 4.3x to 12.5x. However, there is potential for even
greater gains as the current OpenTitan utilizes a fraction of the accelerator
bandwidths, which ranges from 16
accessed and the accelerator used. Our results open the way to the optimization
of OpenTitan-based secure platforms, providing design guidelines to unlock the
full potential of its accelerators in secure applications.
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