High-Performance QC-LDPC Layered Decoder Based on Shortcut Updating

Zhongyong Wang, Zhaoyan Xie,Kexian Gong,Jin Yan, Lianghui Chen

IEEE SIGNAL PROCESSING LETTERS(2024)

Cited 0|Views3
No score
Abstract
Quasi-cyclic low density parity check (QC-LDPC) is widely used in various modern communication standards due to its excellent performance and convenient hardware implementation, but its commonly used pipelined layered decoder faces update conflicts that lead to performance degradation. This letter proposes a shortcut-based decoder to mitigate this problem. When the conflicts occur, we avoid the read/write operations of the log-likelihood ratios (LLRs) and abandon the use of the barrel shifters, and feed those LLRs directly to the next layer. we also attempt to utilize the latest messages for inevitable conflicts. Moreover, the proposed architecture significantly reduces the possibility of conflicts by reordering the base graph matrix (BGM) with a shorter update interval of LLRs, which can achieve maximum utilization in the updated messages. Compared to the state-of-the-art approach in the case of DVB-S2, the proposed architecture can deliver up to 0.25 dB performance gain with faster convergence.
More
Translated text
Key words
Decoding,Parity check codes,Phase change materials,Random access memory,Schedules,Signal processing algorithms,Pipelines,Layered decoder,pipeline conflicts,quasi-cyclic LDPC,shortcut updating
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined