Minimization of DC-Link Ripple Current for Enhancing Reliability in Three-Level Voltage Source Inverters

This paper proposes a DC-link ripple current minimization strategy to enhance the reliability of three-level voltage source inverters (3L-VSIs). The largest current among the three-phase currents flows through DC-link capacitors when a conventional space vector pulse width modulation (SVPWM) is applied to the 3L-VSIs. The large DC-link ripple current generates high heat losses in the DC-link capacitors, which shortens their lifetime and ultimately reduces the reliability of the 3L-VSIs. To mitigate the problems caused by the large DC-link ripple current, the proposed strategy substitutes the small vectors in the switching sequences of the conventional SVPWM with large vectors. As the large vectors induce zero DC-link ripple currents, the minimized DC-link ripple currents and resulting extended lifetime of DC-link capacitors can be attained with the proposed strategy. In addition, the proposed strategy guarantees the voltage balancing of the DC-link capacitors, which is essential in the operation of 3L-VSIs. The performance and feasibility of the proposed strategy are demonstrated by simulation and experimental results.