A Target-Read Retry Scheme for 3D Charge Trap NAND Flash Memory

We propose a target-read retry (TRR) scheme to reduce bit error rate (BER) beyond the conventional read-retry method. The low-bound (LB) and high-bound (HB) tails of cells’ threshold voltage (Vt) distribution, which are vulnerable to read errors, are found to possess a strong and unique neighboring data pattern dependence. Accordingly, a simple neighboring pattern recognition technique is disclosed to efficiently identify the "target" bits for read-retry. The feasibility and effectiveness of the TRR scheme are demonstrated in a 96-layer 3D NAND chip. Dependence of the failure bit count (FBC) evolution with respect to the 1 ^st read voltage (Vr), the neighboring pattern judgement level (V NPJ ), and the capability of read-retry for reducing error bits are clarified. We also apply a simplified model to estimate the BER reduction. Another 38% BER reduction and around 3X retention time extension are achieved by the proposed TRR scheme under practical conditions.