High-performance and low parasitic capacitance CNT MOSFET: 1.2 mA/μm at VDS of 0.75 V by self-aligned doping in sub-20 nm spacer
2023 International Electron Devices Meeting (IEDM)(2023)
Abstract
For the first time we report degenerate and self-aligned doping in the sub-20nm spacer region on a high-density CNT channel to achieve high-performance CNT p-MOSFET with I
D
= 12 mA/μm at V
DS
= -0.75 V, CGP = 160 nm, and L
G
= 50 nm. The extension doping lowers the effective energy barrier height near the contact from 228 meV to 50 meV. The parasitic resistance remains 250 Ω•μm for contact lengths ranging from 100 nm to 20 nm. Calculated intrinsic gate delay (τ=RC=CV/I, including gate and spacer capacitances) based on resistance and spacer capacitance values of experimental structures, indicate that the doped-spacer MOSFET enables intrinsic gate delay ~2× lower vs. SBFET and ~2.6× lower vs. undoped-spacer MOSFET. These benefits are even more significant for shorter channel lengths. Strategies for overcoming channel quality and gate interface non-idealities are discussed.
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Key words
Low Capacity,Carbon Nanotubes,Parasitic Capacitance,Low Parasitic Capacitance,High-performance Carbon Nanotube,Energy Barrier,Resistant Parasites,Electron Beam Lithography,Electron Beam Evaporation,Atomic Layer Deposition,Extensive Regions,Reactive Ion Etching,Doping Effect,Gate Dielectric,Higher Ion,Interface Trap,Subthreshold Slope,Gate Stack
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