Scaling the SOT track – A path towards maximizing efficiency in SOT-MRAM
2023 International Electron Devices Meeting (IEDM)(2023)
摘要
We demonstrate, for the first time, the functionality of a scaled perpendicular spin-orbit torque (SOT)-MRAM where the SOT layer and magnetic tunnel junction (MTJ) pillar exhibit comparable dimensions. This novel design leads to a significant reduction in the power consumption (63% decrease), an enhancement in endurance (>10
15
cycles), and a reduction in bit-cell area. Systematic investigations on device scaling are performed, highlighting the importance of SOT track scaling as a path to enhance the device performance by eliminating power consumption outside the MTJ pillar region. Furthermore, the hybrid free layer stack design offers a potential solution for scaling MTJ dimensions, as it enables low switching current and sufficient retention down to 20 nm.
更多查看译文
关键词
Spin-orbit Torque,Endurance,Power Consumption,Device Performance,Current Switching,Tunnel Junction,Free Layer,Significantly Improved,Length Scale,Integration Process,Hysteresis Loop,Bit Error Rate,Conventional Devices,Technology Node,Track Width
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要