High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies

Tsung-En Lee,Hung-Li Chiang, Chih-Yu Chang,Yuan-Chun Su,Shu-Jui Chang, Jui-Jen Wu, Bo-Jiun Lin,Jer-Fu Wang, Shu-Chih Haw,Shang-Jui Chiu, He-Liang Ching,Yan-Gu Lin,Wei-Sheng Yun,Chen-Feng Hsu, Hengyuan Lee, Tung-Ying Lee,Matthias Passlack,Chao-Ching Cheng, Chih-Sheng Chang,H.-S. Philip Wong,Wen-Hao Chang,Meng-Fan Chang, Yu-Ming Lin,Iuliana P. Radu

2023 International Electron Devices Meeting (IEDM)(2023)

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摘要
For the first time, we demonstrate a transition metal dichalcogenide (TMD) Ferroelectric Field-Effect Transistor (FeFET) with ultra-high endurance (>10 12 measured) and retention time exceeding 10 years. The devices consist of an ultrathin Hf-Zr-based (HZO) ferroelectric deposited by ALD on a stack of AlO x /MoS 2 with process temperature <250°C. By using a 2.5nm HZO layer and a monolayer (1L) MoS 2 , a record-low operating voltage < 1V is reported thanks to excellent gate control. The device fabrication is compatible with Back-End-of-Line (BEoL) processes in advanced CMOS technologies. Array-level projections show that a sufficient memory window is maintained at a supply voltage (V DD ) of IV. This device has promise for high-density memory embedded in scaled CMOS technology nodes.
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关键词
Open Voltage,CMOS Technology,Ferroelectric Field-effect Transistor,Scaled CMOS Technologies,Technological Advances,Transition Metal Dichalcogenides,Atomic Layer Deposition,Monolayer MoS2,Memory Window,X-ray Photoelectron Spectroscopy,I-V Curves,Forward Error Correction,X-ray Absorption Spectroscopy,Non-volatile Memory,Switching Voltage,Gate Bias,X-ray Reflectivity,Subthreshold Swing,High Endurance,Ferroelectric Layer,Ferroelectric Memory,Gate Stack,Sense Amplifier,Word Line
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