Efficient Training Spiking Neural Networks with Parallel Spiking Unit
CoRR(2024)
摘要
Efficient parallel computing has become a pivotal element in advancing
artificial intelligence. Yet, the deployment of Spiking Neural Networks (SNNs)
in this domain is hampered by their inherent sequential computational
dependency. This constraint arises from the need for each time step's
processing to rely on the preceding step's outcomes, significantly impeding the
adaptability of SNN models to massively parallel computing environments.
Addressing this challenge, our paper introduces the innovative Parallel Spiking
Unit (PSU) and its two derivatives, the Input-aware PSU (IPSU) and Reset-aware
PSU (RPSU). These variants skillfully decouple the leaky integration and firing
mechanisms in spiking neurons while probabilistically managing the reset
process. By preserving the fundamental computational attributes of the spiking
neuron model, our approach enables the concurrent computation of all membrane
potential instances within the SNN, facilitating parallel spike output
generation and substantially enhancing computational efficiency. Comprehensive
testing across various datasets, including static and sequential images,
Dynamic Vision Sensor (DVS) data, and speech datasets, demonstrates that the
PSU and its variants not only significantly boost performance and simulation
speed but also augment the energy efficiency of SNNs through enhanced sparsity
in neural activity. These advancements underscore the potential of our method
in revolutionizing SNN deployment for high-performance parallel computing
applications.
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