A High-Speed Low-Power Two-Stage Comparator with Regeneration Enhancement and Through Current Suppression Techniques.

This paper presents a high-speed low-power two-stage dynamic comparator for SAR ADC. The pre-amplifier of the proposed comparator uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback ability. The tail current source is replaced by the input pair to save power. The auxiliary input pair speeds up the regeneration of the latch. Simulation results demonstrate that the proposed comparator with $V_{DD}=1.8\mathrm{V}$ achieved a clock-to-Q delay of 228 ps and an input-referred noise of 479 $\mu \mathrm{V}$ at $V_{id}=1\text{mV}$ and $V_{CM}{=}$ 0.9 V. The proposed comparator consumes 196.3 $\text{fJ}$ per comparison with 1.024 GHz.