Inverse design of high efficiency and large bandwidth power splitter for arbitrary power ratio based on deep residual network

In this research, we propose the deep Residual Network to realize the inverse design of a low loss 1 × 3 port power splitter with an area of 2.6 × 2.6 μm 2 on a standard silicon-on-insulator platform. Then the area is used as the inverse design region and discretized into 20 × 20 square pixels, where each pixel can be switched between the two random initial states of silicon square with and without holes. Besides, we use the direct binary search algorithm to change the state of the pixels so that the distribution of all pixels in the inverse design region reaches the optimal value of the algorithm. While training the network, inputting spectral transmission response, and using the etched hole vector positions as a label for the inverse design, it achieved an accuracy of 0.9111 and a correlation coefficient greater than 0.88 for all three ports. Finally, we demonstrated 1 × 3 power splitters with 1:2:1, 1:2:1.5, 1:3:1, and 1:3:2 distribution ratios and a more than 90% maximum transmission efficiency with bandwidth from 1450 to 1650 nm while having a low insertion loss of less than 0.45 dB. This research can be found potential applications in the design of photonic devices with high performance and small size.