Integrated Wideband Self-Interference Cancellation Techniques for FDD and Full-Duplex Wireless Communication

The continued demand for higher levels of wireless access and increased data rates for a variety of applications from mobile smart phones to back haul point-to-point communication, continues to drive research that enables new spectrum opportunities, reduces form factor and lowers the cost of hardware solutions. The current RF spectrum, which is often referred to as the frequency band from 1-6GHz, has become increasingly crowded with only a limited amount of unused and unlicensed spectrum. This dissertation explores and implements, single-chip hardware front-end solutions which the specific aim to increase data rates for each single-user using two techniques: a. Using In-band full-duplex radio techniques with self-interference cancellation; b. High-speed communication using large bandwidths available at mmWave frequencies. The advantages, challenges and achievements associated with the two proposed techniques will be described in the following paragraphs. First, in-band full-duplex communication potentially increases spectral efficiency within existing RF standards. This will allow the combination of dedicated transmitting and receiving bands into a single band which would more than double the spectral efficiency. However, this leads to an extremely challenging problem associated with transmitter self-interference cancellation. To date, two full-duplex chips have been designed, fabricated and tested, each with a self-interference cancellation function. The first IC is an analog full-duplex front-end for Bluetooth (BLE) applications. Inside the proposed chip, a self-interference cancellation (SIC) circuitry, a low-power receiver, combined with a harmonic-rejection power amplifier (HRPA) are implemented to reduce the transmitter-to-receiver self-interference, and enable full-duplex operation. These techniques were applied towards the realization of a prototype silicon device which implements a tunable self-interference mitigation canceller function with a current-mode LNA and passive-mixer based front-end, and a power amplifier topology to reduce out-of-band emissions. This chip was fabricated in 40nm 6-metal stack CMOS process to achieve more than 30dB measured self-interference cancellation over 4MHz bandwidth, and an integrated power amplifier (PA) which suppresses the 3rd and 5th harmonics by 30dB and 15dB, respectively. The PA delivers a maximum output power of +14dBm with a drain efficiency of 33%. The self-interference cancellation circuitry utilizes an active area of 131×112.5 µm2, has a power consumption of 0.25mW, and degrades the receiver noise figure (NF) by less than 0.6dB. The second IC is a transceiver front-end, which includes a dual-injection path self-interference (SI) cancellation circuitry to enable wideband full-duplex communication with a high-power transmitter. The proposed SI cancellation circuitry is implemented using: (1) one feedforward cancellation path containing a 5-tap analog adaptive filter (AF) between the transmitter (TX) output and the receiver (RX) input; (2) a second cancellation…