A complementary ternary inverter based on the line tunneling field effect transistors

A novel line-tunneling field effect transistor (LTFET) incorporating a reversed p-i-n structure is introduced. The line-tunneling process provides high ION and low SS while the reversed p-i-n structure keeps the IOFF independent on the gate voltage. The inclusion of this mixed conduction mechanism renders the proposed device well-suited for designing complementary ternary logic based on the off-state current mechanism. The designed ternary inverter with low static power dissipation is suitable for the emerging neuromorphic applications where low power is extremely significant. In addition, the proposed device only involves two kinds of conventional Si and Ge materials. In comparison to other devices, such as nanowire or nanotube devices, the suggested planar device structure is notably simpler. Consequently, the device and the ternary inverter are easier to be fabricated and more compatible with the CMOS process platform.