DDQ-APUF: A Highly Reliable Arbiter PUF Using Delay Difference Quantization

Arbiter PUF (APUF) is one of the most well-known physical unclonable functions (PUFs). However, its hardware implementation has poor reliability on field programmable gate arrays (FPGAs). This paper proposed a highly reliable APUF that uses a multi-bit response delay difference quantization strategy (DDQ-APUF). By adding multiple configurable delay units to the two symmetrical circuits of the conventional APUF, the delay difference between the two symmetrical paths of the APUF can be determined by collecting the output of the APUF with different delay configurations. Moreover, a threshold is used to accommodate the variations in delay differences due to environmental variations. This method greatly improves the reliability of the APUF while achieving a high efficiency. The DDQ-APUF was implemented on Xilinx Artix-7 FPGAs and the experimental results show that the reliability achieves 99.95%.