Design of Lightweight Strong Arbiter PUF Circuit Based on MOSFET Threshold Loss.

Arbiter Physical Unclonable Function (APUF), as a typical representative of strong PUF, suffers from limitations in hardware cost and randomness, severely constraining its application in the field of resource-constrained Internet of Things (IoT). This paper investigated the mechanism of MOSFET threshold loss and proposed a lightweight strong APUF structure of two kinds of MOSFETs. This structure utilizes the threshold loss that occurs when PMOS transmits low level and NMOS transmits high level, greatly extending the delay deviation of the rising and falling edges, thus enhancing the randomness of the PUF and passing 9 NIST randomness subtests. Each delay unit of the two proposed PUF circuits consists of only 16 MOS transistors, which is 8 transistors less than the delay unit of APUF. The full-custom layout area of the proposed delay unit is 4.68 μm ² in TSMC 65 nm process, reducing the area by 35.8% compared to the traditional APUF.