An Automatic Optimization Method of Combinational Logic Loops in CGRA.

In Coarse-Grained Reconfigurable Arrays (CGRA), there exists combinational logic loops, which generally exist in the form of pseudo paths. Although these loops do not affect the circuit function, they may cause failures in static timing analysis. In this paper, we apply an improved Floyd cycle detection algorithm to optimize the combinational logic loops by inserting registers strategically. In addition, the efficiency of our algorithm is enhanced by pruning and dynamic programming technique, which can reduce unnecessary computations, optimize the search space, and enable efficient memorization of intermediate results. As a result, our algorithm achieves a significant speedup of 1927 times. Comparing our method with the existing approach in TRAM CGRA, we demonstrate a reduction in the number of inserted registers by approximately 44% to 48%. This reduction showcases the effectiveness and superiority of our method in optimizing CGRA, resulting in improved resource utilization and potential performance enhancements.