High-Performance BLS12-381 Pairing Engine on FPGA.

As concerns for security are increasing, more and more applications require a more complicated algorithm that would allow more functionality in the cryptosystem. One of the core algorithms is the pairing-based cryptography (PBC), which relies on the property of pairing function. The computation speed of pairing would be important for realizing many systems in real-world scenarios, such as attribute-based encryption. To showcase the possible hardware acceleration of the pairing operation, we propose a high-performance accelerator, the pairing engine, which is implemented on FPGA. The architecture is adopted from previous ASIC implementation with the proposed new Fp2 modular multiplier and the fine modulo reduction that allow it to run at 180 MHz on FPGA. Our proposed pairing engine can compute the pairing operation on BLS12-381 within 62.2 µs, the fastest ever recorded, which is three times faster than the state-of-art in FPGA while also improving the Normalized Area-Time criteria by half.