Analysis and Design of the Interposer PDN With Optimal Arrangement of Decoupling Capacitors

With the ever-increasing integration density of electronic systems and reduced noise margins, maintaining high power integrity has become a formidable challenge in the design of high-performance 3D integrated circuits (3D ICs). To enhance power integrity, the insertion of decoupling capacitors has proven to be an important and effective solution. However, existing decoupling capacitor optimization approaches, while meeting constraints on input impedance, suffer from a significant overdesign issue. This paper proposes a novel trade-off optimization method for decoupling capacitor assignment in interposers to address power integrity concerns. The method utilizes an immune algorithm to minimize the cost of decoupling capacitors while adhering to constraints on impedance bounds and avoiding over-design. The key enabler for achieving efficient optimization lies in the estimation of the required decoupling capacitor count so that the scope of the search space has been significantly reduced. The proposed method achieves a reduction in decoupling capacitor cost, while also exhibiting a speedup compared to other methods.