Design of Alignment Marker Sequences in Ethernet to Suppress Baseline Wander and Clock Wander

To support high volumes of data transmission, multiline distribution technology is used in both 400 and 800 GbE, which uses alignment markers (AMs) in each line to differentiate them from one another. However, inefficient design of AMs can result in dc-unbalanced, low transition density symbols when they are bit multiplexed, which in turn results in large baseline wander (BW) and clock wander (CW) of the received signal. In this article, we introduce two new metrics-attenuation cumulative sum (ACS) and generalized transition balance (GTB). Using the two new metrics ACS and GTB, we efficiently design AMs for the 400GBASE-R and 800GBASE-R framework in 400 and 800 GbE, respectively. We show through numerical simulations that the proposed AMs outperform the traditional AMs in terms of BW and CW performance during data transmission.