A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load
IEICE ELECTRONICS EXPRESS(2024)
摘要
This paper proposes a self-biased sub-threshold CMOS voltage reference for ultra-low-power application. In the current generation path, a source degeneration active load (SDAL) is added to reduce the variation of the reference current (IR) which helps to produce a stable voltage reference (VREF). Moreover, by utilizing the line sensitivity (LS) improving circuit, the dependence of VREF on the supply voltage (VDD) can be largely reduced. The proposed design is fabricated ina standard 0.18-mu m CMOS process. 11-chip measurement results show the prototype design can provide an 147.1 mV average voltage with a minimum power consumption of 353 pW at 27 celcius. The line sensitivity (LS) is only 0.014%/V, while the power supply rejection ratio (PSRR) at 10 Hz is-68 dB. The average temperature coefficient (TC) is 72 ppm/degrees C from-20 C-degrees to +80 C-degrees, and the die area is only 0.0019 mm2.
更多查看译文
关键词
CMOS voltage reference,line sensitivity,low power,self-biased
AI 理解论文
溯源树
样例
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要