Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration.
2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)(2023)
摘要
This paper addresses the need for customizable processor architectures by presenting the design and implementation, on both FPGA and ASIC devices, of a flexible RISC-V in-order pipeline core. The study expands the design space exploration possibilities by introducing a customizable number of stages in the pipeline architecture. The methodology leverages the fundamental building blocks of non-pipelined architectures while incorporating different interconnections and a specific control unit. Through evaluation and analysis, this study provides insights into the impact of pipeline architecture on performance, while also highlighting the advantages of non-pipeline processors in architecture design. The findings contribute to the field by enabling the identification of the optimal architecture, considering application constraints and target technology, in the domain of size-optimized and low-power CPUs.
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关键词
CPU,RISC-V,RTL,Pipeline,Flexibility,Modularity,FPGA,ASIC,Design Space Exploration
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