Modeling the Parasitic Resistances and Capacitances of Advanced Vertical Gate-All-Around Transistors

This article presents the parasitic capacitance and resistance models specifically for advanced vertical gate-all-around (VGAA) nanosheet FETs. By combining regional analysis with the three fundamental capacitance modules, the parasitic capacitance components are defined and subsequently modeled individually. The parasitic resistance is also divided into components based on the current path analysis. By combining the modified transmission line method, spread, and thin film resistance formulations, a comprehensive resistance model is worked out covering structural parameter variations. In addition, the model also considers possible VGAA layouts, namely, the L type and Line type. The developed parasitic models have undergone extensive verification across a broad spectrum of parameters, confirming their accuracy and scalability. The proposed models were implemented into the calibrated Berkeley short-channel IGFET model (BSIM)-CMG models, facilitating the prediction of circuits such as ring oscillators, and their implications on the unique asymmetric source-drain structure are also discussed. This work provides strategic guidance for the design technology co-optimization of advanced VGAA technology.