A High-Throughput QC-LDPC Encoder

Low Density Parity Check (LDPC) codes have been widely used in communication and storage fields to support high reliability of data channel. Quasi-cyclic (QC)-LDPC as a regular code can sufficiently exploit hardware parallelism of Field-Programmable Gate Array (FPGA) to accelerate the encoding/decoding performance. However, existing FPGA encoders are generally dedicated to a specialized LDPC code and hardware platform with limited flexibility. In this paper, to achieve high throughput and flexibility simultaneously, we propose a High-level synthesis (HLS) based QC-LDPC encoder microarchitecture. The encoder designs a fine-grained partially-parallel iterative process execution to exploit intra-codeword parallelism by fully leveraging capability of HLS. The proposed encoder further optimizes data-layout and HLS-function implementation. The encoding throughput of the proposed encoder achieves 98.4Gbps higher than the state-of-the-art QC-LDPC encoder by up to 14.75x.