On improving the critical path delay of PathFinder at smaller channel widths.

2023 22nd International Symposium on Communications and Information Technologies (ISCIT)(2023)

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摘要
PathFinder, a popular FPGA routing tool, employs negotiated congestion routing that reduces the congestion by forcing the nets to detour through uncongested interconnects. However, such detouring often gives less importance to the delay of the interconnects and more to their congestion. This approach may increase the critical path delay (CPD) under tight capacity constraints. In this work, we propose a historical cost function for the negotiated congestion routing that ensures solutions have small CPD values. The proposed historical cost function is integrated into the latest version of PathFinder, and its performance is evaluated using Titan23 FPGA benchmarks. The results indicate that the proposed cost function can enable PathFinder to converge to solutions of smaller CPD, even for small channel widths. Statistical tests are employed to verify the significance of the benefits of the proposed approach.
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关键词
FPGA,routing,negotiated congestion,electronic design automation,intelligent manufacturing
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