Suppressing Threshold Voltage Drift in Sub-2 nm In₂O₃ Transistors With Improved Thermal Stability

Ultrathin In(2)O(3 )films with a thickness of less than 2 nm have emerged as highly intriguing semiconductor channels owing to their exceptional electronic properties. However, their process reliability, particularly the challenge of threshold voltage ( V-T ) drift during gate-stack processing, hinders their potential applications in back-end-of-line (BEOL). This study explores the V-T shift induced by stacked HfO2, showing both thermal atomic layer deposition (T-ALD) and plasma-enhanced atomic layer deposition (PE-ALD) cause significant V-T shift in ultrathin In2O3. To mitigate V-T shift, we introduce a pre-dielectric stacking, solution-based treatment, which can effectively passivate oxygen-related defects in ultrathin In2O3, maintaining V-T without adversely affecting electrical properties. Utilizing this technique, we have successfully demonstrated the first top-gate In2O3 transistor without the requirement of post-fabrication annealing to uphold the on/off ratio. The developed top-gate device also exhibits superior thermal stability, suggesting its potential for future monolithic 3D integration applications.