A 400uW 3.6GHz-4.6GHz Low Power Cryogenic CP-PLL with Transformer-Based VCO in 28nm Bulk CMOS.

A 400uW 3.6GHz - 4.6GHz low power interger-N CP-PLL working down to 3.5K is proposed for quantum applications. It has minimal power consumption owing to its utilization of a source-switching charge pump, coupled with a low current bias transformer-based VCO that ensures enough output amplitude. The proposed PLL is fabricated in 28-nm Bulk CMOS process. Under 3.5K temperature, the PLL achieves 2.17ps jitter @4GHz with -70 reference spur consuming only 400uW power consumption and the FOM is -237dBc/Hz.