Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates

Ternary logic system has attracted more and more attention because of its higher information density as compared with the binary system. In the prevalent multi-threshold-based ternary logic synthesis method, carbon nanotube field effect transistors (CNTFETs) are intensively utilized to realize various ternary logic circuits due to the convenient control of threshold voltages. However, a general ternary logic gate requires three kinds of threshold voltage, whose specific values needs to be determined to optimize the delay and power performance. In this paper, an unbalanced ternary full adder based on ternary cycling gates is presented. Beneficial from the ternary arithmetical algorithm, the circuit complexity of the ternary adder has been largely simplified with only 93 transistors involved, which is much less than previous works. Besides, the optimal threshold voltage combination method has been investigated to optimize the circuit power-delay-product (PDP), and the lowest PDP of 12.55 aJ is achieved.