A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor.

Ring-oscillator based BBPLL is widely used in clock generators for its simplicity. However, satisfying the jitter requirement under various PVT conditions is not easy and thus worst case design is usually employed with many iterations of fabrication and testing, which leads to waste of power in normal conditions and delayed time-to-market. Although several works have tried to minimize the variation of jitter or PLL loop bandwidth [1], [2], the output jitter cannot be set as desired and thus worst case design and iterations are still necessary. In this work, we propose a BBPLL whose jitter can be set to a desired target value. It employs a stochastic jitter monitoring circuit (JMC) and automatic loop gain control (ALGC) that allows the PLL to optimize its power and bandwidth to achieve the target rms jitter.