A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge.

With the ever-increasing bandwidth of memory interfaces, including GDDR, securing link margins is becoming more critical. Starting with the production of memory that employs Pulse Amplitude Modulation-4 (PAM4) such as GDDR6X, each memory manufacturer aims at designing a robust interface with PAM4 signaling. However, direct test equipment is not available to verify the operation of the memory with the controller. For example, T5511 (ADVANTEST) Tester, an existing test solution using Automatic Test Equipment/System Level Test (ATE/SLT), does not support PAM4 signaling and testable data rates are limited to 8 Gbps. Therefore, development of innovative methods such as the Built-Out Self-Test chip (BOST) chip [1] is being designed to ease the high-speed testing as well as reducing the increased cost of new test equipment. Moreover, in the previous work [2], constant impedance matching was achieved by applying the current mode type of the PMOS input to the PAM4 TX operating at high speed. However, testing the memory requires adjustable tuning of the Ratio of Level Mismatch (RLM) as well as impedance matching. In this paper, we propose an optimal bridge architecture with all necessary functions that satisfies the extended function and higher bandwidth in conjunction with existing test equipment. In addition, we describe the method of output level adjustment in the PAM4 driver for improved the RLM. The bridge operates at 48 Gbps per pin and consumes 1.85 pJ/bit and 2.97 pJ/bit for write and read modes of the PAM4 memory, respectively.