A 102.1-dB SNDR oversampling merge-mismatch-error-shaping SAR ADC in 180 nm CMOS

In this paper, we propose a merge-mismatch-error-shaping (M-MES) noise shaping SAR ADC as a solution to address the limitation of SNDR caused by the non-linearity resulting from DAC mismatch. The proposed M-MES technique is based on MES with the introduction of capacitive merging to mitigate the degradation of dynamic range (DR) in ADCs. In addition, to meet the high signal-to-noise ratio (SNR) and low power requirements of the ADC, cascaded integrator feed-forward (CIFF) noise shaping ADC in this paper is a first-order filter based on a closed-loop amplifier. The proposed ADC was simulated and designed in a 180-nm CMOS process, which consumes 449 mu W of power when operating at 1 MS/s sampling frequency. According to the post-simulation results, under a 3.3-V supply and at an oversampling ratio (OSR) of 500, the proposed ADC achieves Schreier FoMS of 168.5 dB with 102.1 dB signal to noise and distortion ratio (SNDR) and 102.2 dB spurious free dynamic range (SFDR).