Combinational logic circuits based on a power- and area-efficient memristor with low variability

The saturation of complementary metal–oxide–semiconductor (CMOS) technology in terms of area and power efficiency has given rise to advanced research on nanodevices. Memristors and their switching properties facilitate the implementation of various combinational logics and neural networks by potential replacement of the existing CMOS technology for edge computing devices. This work presents the design, implementation, and performance evaluation of memristor-based combinational logic circuits including adders, subtractors, and decoders via MATLAB Simulink and Cadence Virtuoso. In this work, we propose an optimized design of memristor-based combinational logic circuits and conduct a comparative study with the conventional method. The proposed memristor model is thoroughly validated experimentally for a high-density Y 2 O 3 -based memristive crossbar array and shows ultralow values in device-to-device and cycle-to-cycle variability. The power calculated from these circuits is reduced by more than 90% as compared to conventional CMOS technology implemented in Cadence Virtuoso. Moreover, the number of components utilized in the memristor-based logic circuits is significantly reduced in comparison to existing CMOS technology, which makes it more area-efficient and opens new avenues for the design and implementation of complex logic circuitry in few-micrometer scale.