(Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the DTCO compact models [1]. As an important first step to access the intrinsic device characteristics, one must remove or ‘de-embed’ the parasitic contributions of external test structures and interconnections. However, for technologies such as the 3D VNWFET, precision of the S-parameter de-embedding step is crucial for accurate model parameter extraction. On the current fabricated VNWFET wafer, only open structures were available and the standard open de-embedding method led to inaccurate or even unphysical values of intrinsic capacitances. While one could design and fabricate additional de-embedding test structures to overcome this, to avoid another design cycle, a new dedicated de-embedding method was developed based on the modelling of the transistor interconnects, leveraging EM simulation [2]. After accurately calibrating the EM simulation against S-parameter measurements of the Open structure, virtual test structures of the same technological process, layout and material properties, were designed in the EM simulation environment. This included Open and Short structures at different reference planes that were simulated for extracting individual interconnect parasitic contributions. Next, the EM simulation served as a predictive tool to construct an electrical equivalent circuit of the entire 3D VNWFET interconnection network (Fig.1). Compared with conventional de-embedding techniques based on Open and Short measurements, the proposed interconnect network modelling-based approach relies on fewer test structures and can provide better accuracy, necessary for compact model parameter extraction. The DTCO is driven by the use of VNWFETs in highly compact 3D logic circuits. Design of these logic circuits relies heavily on compact models, containing a set of physics-based analytical equations for the juntionless transistors. The compact model developed for the 18 nm VNWFET technology [3] has been extensively validated against measurements depicting very good agreement over the entire bias range. To leverage the model for predictive design through DTCO, we further explored the scalability for all available transistor geometries that showed a visible improvement in current scalability for larger devices (Fig.2). However, process variation has limited linear current scaling in smaller nanowire diameters that are of more interest for junctionless transistor operation. In contrast, for a given number of parallel nanowires, maintaining gate electrostatic control over the channel in larger diameters becomes more difficult along with a degradation of the drain current on/off ratio, despite better current scaling (Fig.3). So as a design trade-off for the DTCO, we chose transistors with an optimal diameter (where junctionless functionality and gate electrostatic control are maintained for individual nanowires) with a higher number of nanowires in parallel to boost the drive current. Reliability assessment through electro-thermal measurements of VNWFETs is crucial when designing 3D logic circuits within DTCO framework, particularly for evaluating long-term performances and underlying transport mechanisms. Conventional methods for thermal investigation were not applicable for the VNWFETs as the drain current shows steady increase with temperature in contrast with classical devices (Fig.4). Since activation of self-heating could not be confirmed using traditional methods, a new methodology for thermal resistance estimation in VNWFETs is developed. This relies on the intersecting points on I D -V G curves at different measurement temperatures (T A ) and power dissipations (P diss ) corresponding to same V G and I D . From the ratio of junction temperatures (T j =T A +R TH *P diss ) for the two sets of intersecting curves related to different V D and threshold voltages and subsequent calculations, thermal resistances (R TH ) were extracted. Theoretical calculations corroborated extracted results with R TH values ranging between 4 and 28×10 4 K/W. Other non-conventional methods were also explored such as low-frequency S-parameter measurements or R TH extraction using the slope of drain current versus temperature plot at different dissipated powers, all of which offered similar results even though measurement uncertainties related to each method should be carefully accounted for. A final verification using full device thermal simulation in COMSOL multiphysics, accounting for both ballistic and diffusive heat flux, showed fair agreement with experimental results. This is the first demonstration of thermal resistance extraction in highly-scaled VNWFETs. Figure 1