Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ISUBON/SUB) can be increased by highly localized point tunneling while suppressing off-current (ISUBOFF/SUB) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ISUBON/SUB/ISUBOFF/SUB) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.