Backside Fault Localization and Defect Physical Analysis of Degraded Power HEMT p-GaN Transistors Stressed in DC and AC Switching Modes

This paper describes a backside approach methodology for sample preparation, fault localization and physical defect analysis on p-GaN power HEMT electrically stressed in DC voltage surge and AC switching mode. The paper will show that preparation must be adapted according to the defect position (metallurgy, dielectric layers, epitaxy, etc.) which depends on the type of stress applied. In our life-operation mode amplified electrical stress reliability study, the failure analysis will help us to reveal the weakest parts of the transistor design in relation to the type of applied stress. The failure analysis presented in this paper is composed of electrical characterization, defect localization with PEM and LIT, FIB Slice&View, TEM analysis and frontside conductive AFM after a deep HF.