Optimised Serial Commutator FFT Architecture in Terms of Multiplexers

This brief introduces an optimised architecture for a serial commutator (SC) pipelined fast Fourier transform (FFT) with fully real data paths, utilising a novel data management scheme based on bit-dimension permutation circuits. By employing this approach, we minimised multiplexer utilisation by 80% in every processing element (PE) and 50% in every permutation circuit of each stage compared to the conventional SC architecture. Additionally, the proposed structure achieved full hardware utilisation with a natural-order input/output (I/O) datastream. Experimental results demonstrate that our architecture reduced look-up table (LUT) logic by 31% compared to the prior design.