Recording channel design for time-based measurements in 28 nm CMOS

In this paper we present a recording stage dedicated to time-based measurements required in imaging detectors. The prototype ASIC is manufactured in the 28 nm CMOS process and consists of a 8 x 4-pixel matrix of 50 mu m pitch. Each pixel includes a recording stage that processes input signals for the digital circuitry, responsible for performing time-based measurements such as Time-over-Threshold and Time-of-Arrival. The digital part of the pixel is made up of two ring-based oscillators, configuration registers, and counters. The recording channel occupies only 12 x 50 mu m while consuming 4.5 mu A current. The in-pixel coarse and fine correction methods implemented allowed an improvement of gain and offset uniformity 3.3 and 10 times, respectively.