Quality control testing of the HCC ASIC for the HL-LHC ATLAS ITk strip detector

Abstract The high-luminosity upgrade to the LHC requires a new silicon-strip charged-particle tracking detector for ATLAS. The HCC (Hybrid Controller Chip) is one of three new radiation-tolerant ASICs for this silicon-strip detector. As the interface to multiple binary readout ASICs, the HCC is responsible for buffering and forwarding control signals and readout requests to them as well as serializing their readout data into a 640 Mbps output. All HCCs undergo a suite of tests to verify their analog and digital functionality. The yield for the HCC exceeds the 90% target for production.