A 20 MHz, 98.7 dB-SFDR, Capacitively Degenerated Dynamic Amplifier Without Bias Voltage Calibrations.

Capacitively-degenerated-linearization (CDL) dynamic amplifier has superior linearity, which is appropriate to act as a residue amplifier in pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs). However, the traditional CDL amplifier is very sensitive to its bias voltage, which makes it not user-friendly. In order to improve the sensitivity to the change of bias voltage, this brief proposes a high linearity and bias-robust CDL-amp. It no longer needs to calibrate the bias voltage from outside the chip. Instead, an additional mimetic control circuit is introduced to the CDL-amp, which assists in stopping the CDL-amp amplification process at the optimal linearity instant. Thanks to this on-chip mimical circuit, the CDL-amp’s linearity is less sensitive to the bias voltage fluctuations. We perform this design in a 28-nm CMOS process. Post-layout simulation result shows a 98.7 dB spurious-free dynamic range (SFDR) under 20 MHz clock frequency and 1.8 V supply. Compared to the prior art of high linearity dynamic-amp, this design outperforms by about 20 dB in SFDR. The total-harmonic-distortion (THD) is improved by about 7 dB under supply voltage variations and by about 15 dB under input level variations, respectively. Besides, this fully-dynamic amplifier only consumes 48 μW.