(Invited) In-Depth DC and Low Frequency Noise Characterization of Nanosheet FETs at Room and Cryogenic Temperatures

In this work, an in-depth static and low frequency noise characterization of nanosheet FETs, consisting of two vertically stacked silicon channels per device, is performed. A comparison of the performances from n- versus p-channel FETs operated at 300 K and 78 K, in terms of static and low frequency noise parameters variability, is also discussed. The studied devices were fabricated at imec. The geometrical dimensions of the devices are the following: each fin presents a width of 15 nm and each nanosheet thickness is around 11 nm. The effective channel width is calculated as W eff = 2·N·(2·W fin + 2·H fin ), where N is the number of fins in parallel in the layout and per device. The equivalent oxide thickness is around 0.9 nm. Two structures having different vertical distance between the stacked nanosheets: 7.5 nm (wafer#1) and 4.7 nm (wafer#2) are investigated. Overview results focus on devices having a fixed gate length (L G ) of 100 nm and 22 fins in parallel (N = 22) [1,2] but preliminary results on devices having L G = 70 nm and N = 2 are also presented. More information about the device fabrication and the experimental setup used for the various types of measurements covered in this work can be found in [3,4]. Typical drain current and transconductance transfer characteristics for n- and p-channel devices from wafer#1 operated at 78 K are illustrated in Figure 1. The main static parameter extraction of the devices operated in ohmic regime is made comparing two methodologies which are not affected by the access resistance impact, as Y-function [5,6] and the McLarty equations [7] methodologies. Good agreement between the extracted parameters using these two methods is obtained in particular when the simple criteria proposed in [1] are employed. Indeed, criteria in [1] allow to properly choose the applied gate voltage interval for which the parameter extraction using Y-function should be made when the impact of the surface roughness collisions in the mobility expression cannot be neglected. An example of input-referred noise spectra, at different applied gate voltages, for n-channel devices from wafer#1 operated at 78 K is shown in Figure 2. White noise, flicker noise and depending on the polarization one or more Lorentzian noise contributions may be observed on the total input-referred noise spectra for all investigated devices. The noise parameters are estimated using methodologies presented in [4,8]. It is demonstrated that the 1/f noise mechanism may be explained by the carrier number fluctuations correlated to the mobility fluctuations mechanism [9] from weak to moderate inversion operation, while in strong inversion operation the 1/f noise behavior is dominated by the access resistances noise [10] contribution. It is shown that the access resistance parameter is the key parameter in order to not underestimate the Coulomb scattering coefficient value. Overall, we have found that the wafer#1 devices present good electrical properties in terms of mobility, threshold voltage, access resistance and even from a flicker noise level point of view, for both n- and p-channel nanosheet FETs, while devices from wafer#2 with a smaller separation between the nanosheets suffer more from mobility variability and high access resistances due to a non-optimized process flow. References : [1] Cretu et al., accepted in IEEE Trans. Electron Dev. [2] Cretu et al., Solid-State Electron, 2022, 194, pp. 102-108, 108209, DOI: 10.1016/j.sse.2022.108360. [3] Veloso et al., SSDM Tech. Dig., 2019, pp. 559-560, DOI: 10.7567/SSDM.2019.N-1-03. [4] Boudier et al., Solid-State Electron, 2017, 128, pp. 102-108, DOI: 10.1016/j.sse.2016.10.012. [5] Ghibaudo, Electronics Letters, vol.24, no. 9, p. 543, 1988, DOI: 10.1109/ICMTS.2000.844428. [6] Mourain et al., ICMTS 2000, pp. 181-186, 2000, DOI: 10.1109/ICMTS.2000.844428. [7] K. McLarty et al., Solid-State Electron., 1995, 38 (6), pp. 1175-1177, DOI: 10.1016/0038-1101(94)00248-E. [8] Boudier et al., Solid-State Electronics, vol. 168, DOI : 10.1016/j.sse.2019. [9] Ghibaudo et al., Phys. Status Solidi (a), 1991;124 (2), pp. 571-581, DOI : 10.1002/pssa.2211240225.D..107732. [10] F.N. Hooge, IEEE Trans. Electron Dev. 41, pp. 1926-1935, 1994. DOI: 10.1109/16.333808. Figure 1